1. Field of the Invention
The invention relates in general to a substrate and a package and methods of manufacturing the same, and more particularly to the substrate having a single patterned metal layer, and a package applying the substrate, and methods of manufacturing the substrate and the package.
2. Description of the Related Art
The integrated circuit (IC) package technology plays an important role in the electronics industry. Electronic packaging is for protecting and supporting circuit configuration, creating a path for heat dissipation and providing modularized standard specification form factors for the parts. Electronic packaging in 1990s mainly employs ball grid array (BGA) packaging which is excellent in heat dissipation, has excellent electrical properties and is capable of increasing leads and effectively reducing the surface area of the package.
As lightweight, thinness, compactness, and high efficiency have become universal requirements of consumer electronic and communication products, the chip requires superior electrical properties, a smaller overall volume, and a larger number of I/O ports. As the number of I/O ports increases, the pitch of the integrated circuit is reduced. Thus, it is very difficult to achieve a high efficiency wiring on a BGA substrate or a lead frame substrate. For example, the density of I/O ports increases dramatically starting with the 0.18 μm IC node or high speed (such as 800 MHz above) IC design. Flip chip technology, having high I/O density and excellent electrical properties, is a solution to the above problem and has become one of the mainstreams in the development of electronic carriers. It is a main goal for the manufacturers to develop a substrate with higher density of I/O ports, smaller trace pitches and excellent electrical properties. Besides, in addition to the request of the flip chip technology, the request of systematic integration of the downstream products is also getting more and more urgent. Thus, the multi-chip module (MCM) process has an increased need of the MCM carrier. The MCM carrier and the flip chip carrier have great market potentia.
Along with the maturity in the chip scale packaging (CSP) technology, system in package SiP, the systematic semiconductor integration on a package level, which function-wise and cost-wise, has become a mainstream in packaging technology. As the product size becomes smaller and smaller and the function becomes more and more versatile, the SiP technology is used to satisfy the market demands. SiP technology integrates chips of different functions, passive components and other modules together, so that the electronic products have versatile functions. SiP technology also includes different technologies such as 2-dimensional multi-chip module packages and 3-dimensional stacked packages which stack chips of different functions for saving space. As for what type of packaging is most suitable for an application is determined according to the needs of the application. The SiP technology has a wide range of definition, and employs many types of bonding technologies such as wire bonding, flip chip bonding and hybrid-type bonding.
Take the SiP package for example. The SiP package integrates the dice of different digital or analogue functions and bonds the dice on a chip carrier by way of bump bonding or wire bonding. The carrier having embedded passive components or traces possesses electrical properties and is called the integrated substrate or the functional substrate. FIG. 1A˜FIG. 1F schematically shows a progressive flow of manufacturing of a conventional integrated substrate. First, a copper clad laminate (CCL) having a core 102 sandwiched between the first conductive layer 103 and a second conductive layer 104 is provided, as shown in FIG. 1A. The first conductive layer 103 and the second conductive layer 104 are formed of copper. The copper clad laminate is then drilled to form the through hole 106, as shown in FIG. 1B. Next, copper plating step is performed to plate the copper layer 107 on the surfaces of the first and second conductive layers 103 and 104, and also at the sidewall of the through hole 106′, as shown in FIG. 1C. Afterward, the metal trace formation proceeds. As shown in FIG. 1D, a patterned dry film 108 is formed on each copper layer 107. Next, the copper layer (107+103 and 107+104 respectively) is etched according to the patterned dry film 108 (as a mask), as shown in FIG. 1E. Finally, the patterned dry film 108 is removed, and the metal trace (107+103) is revealed. Also, the subsequent steps could be further conducted to complete the final product. For example, a solder mask (SM) is printed followed by exposing and developing procedures to expose partial surface of the metal trace (107+103), and a surface treatment such as Ni/Au is plated on the exposed surface of the metal trace (107+103).
For another type of integrated substrate, the through hole in the substrate could be filled with the conductive material such as copper by plating procedure, and the copper layers on two sides of the core are then patterned to form the metal trace. FIG. 2 schematically shows an alternative structure of conventional integrated substrate. However, plating procedure for filling the through hole requires more complicated technique and longer time to plate. Also, it is difficult to control the thickness of the copper layers 115, 116 and 117 (especially copper layer 117).
Since the substrate depicted in FIG. 1F or FIG. 2 mainly include a core layer (102/112) sandwiched between “two conductive layers”, it is so called a 2-L substrate.
To satisfy the requirements of small-sized electronic products, it is a trend to develop a substrate structure with high density of I/O ports and small trace pitches without sacrificing the electrical properties. However, it is difficult to further reduce the size of the conventional structures (such as substrates of FIG. 1F and FIG. 2) using the known manufacturing methods. Besides the size and electrical properties, manufacturing cost of the substrate is also a considerable factor in the device application, especially for the small device with lower market price. Thus, it is an important goal for the manufacturers to develop a novel substrate with low (thin) profile, and manufactured by a simplified process, suitable for mass production and maintaining high production yield, so as to satisfy the desired requirements of the electronic product with low profile and low cost.